The present invention relates generally to data processing systems and more particularly to arithmetic logic units included therein.
Some data processors have the capability of operating upon data which is a multiple of, for example, four, eight or sixteen bits, i.e., digits, bytes and words respectively. Such data or operands are available from memory associated with the data processor only on a sixteen-bit or word basis. Further, more data processor instructions operate on two operands which, in general, are of an unequal length. The result of such data processing usually replaces one of the operands. In the processing of instructions of this type, the following requirements should be met. There is a need to locate the starting and end points of data in the memory word. Further, there is a need to step sequentially from one unit of data to the next unit of data. In addition, data must be processed in either direction from the least significant bit to the most significant bit or vice versa, and, in addition, invalid combinations must be detected in one or both operands. Operands of unequal length must also be compensated for in order to provide a correct result.
It is accordingly a primary object of the present invention to provide an improved arithmetic logic apparatus for use in a data processing system.